NMSIS-Core
Version 1.0.0-HummingBird
NMSIS-Core support for HummingBird RISC-V processor-based devices
riscv_encoding.h
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/*
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* Copyright (c) 2019 Nuclei Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __RISCV_ENCODING_H__
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#define __RISCV_ENCODING_H__
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#include "riscv_bits.h"
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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#define MSTATUS_UIE 0x00000001
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#define MSTATUS_SIE 0x00000002
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#define MSTATUS_HIE 0x00000004
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#define MSTATUS_MIE 0x00000008
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#define MSTATUS_UPIE 0x00000010
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#define MSTATUS_SPIE 0x00000020
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#define MSTATUS_HPIE 0x00000040
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#define MSTATUS_MPIE 0x00000080
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#define MSTATUS_SPP 0x00000100
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#define MSTATUS_MPP 0x00001800
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#define MSTATUS_FS 0x00006000
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#define MSTATUS_XS 0x00018000
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#define MSTATUS_MPRV 0x00020000
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#define MSTATUS_PUM 0x00040000
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#define MSTATUS_MXR 0x00080000
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#define MSTATUS_VM 0x1F000000
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#define MSTATUS32_SD 0x80000000
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#define MSTATUS64_SD 0x8000000000000000
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#define MSTATUS_FS_INITIAL 0x00002000
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#define MSTATUS_FS_CLEAN 0x00004000
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#define MSTATUS_FS_DIRTY 0x00006000
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#define SSTATUS_UIE 0x00000001
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#define SSTATUS_SIE 0x00000002
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#define SSTATUS_UPIE 0x00000010
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#define SSTATUS_SPIE 0x00000020
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#define SSTATUS_SPP 0x00000100
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#define SSTATUS_FS 0x00006000
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#define SSTATUS_XS 0x00018000
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#define SSTATUS_PUM 0x00040000
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#define SSTATUS32_SD 0x80000000
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#define SSTATUS64_SD 0x8000000000000000
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#define CSR_MCACHE_CTL_IE 0x00000001
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#define CSR_MCACHE_CTL_DE 0x00010000
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#define DCSR_XDEBUGVER (3U<<30)
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#define DCSR_NDRESET (1<<29)
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#define DCSR_FULLRESET (1<<28)
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#define DCSR_EBREAKM (1<<15)
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#define DCSR_EBREAKH (1<<14)
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#define DCSR_EBREAKS (1<<13)
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#define DCSR_EBREAKU (1<<12)
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#define DCSR_STOPCYCLE (1<<10)
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#define DCSR_STOPTIME (1<<9)
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#define DCSR_CAUSE (7<<6)
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#define DCSR_DEBUGINT (1<<5)
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#define DCSR_HALT (1<<3)
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#define DCSR_STEP (1<<2)
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#define DCSR_PRV (3<<0)
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#define DCSR_CAUSE_NONE 0
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#define DCSR_CAUSE_SWBP 1
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#define DCSR_CAUSE_HWBP 2
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#define DCSR_CAUSE_DEBUGINT 3
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#define DCSR_CAUSE_STEP 4
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#define DCSR_CAUSE_HALT 5
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#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))
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#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))
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#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
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#define MCONTROL_SELECT (1<<19)
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#define MCONTROL_TIMING (1<<18)
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#define MCONTROL_ACTION (0x3f<<12)
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#define MCONTROL_CHAIN (1<<11)
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#define MCONTROL_MATCH (0xf<<7)
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#define MCONTROL_M (1<<6)
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#define MCONTROL_H (1<<5)
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#define MCONTROL_S (1<<4)
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#define MCONTROL_U (1<<3)
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#define MCONTROL_EXECUTE (1<<2)
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#define MCONTROL_STORE (1<<1)
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#define MCONTROL_LOAD (1<<0)
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#define MCONTROL_TYPE_NONE 0
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#define MCONTROL_TYPE_MATCH 2
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#define MCONTROL_ACTION_DEBUG_EXCEPTION 0
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#define MCONTROL_ACTION_DEBUG_MODE 1
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#define MCONTROL_ACTION_TRACE_START 2
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#define MCONTROL_ACTION_TRACE_STOP 3
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#define MCONTROL_ACTION_TRACE_EMIT 4
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#define MCONTROL_MATCH_EQUAL 0
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#define MCONTROL_MATCH_NAPOT 1
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#define MCONTROL_MATCH_GE 2
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#define MCONTROL_MATCH_LT 3
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#define MCONTROL_MATCH_MASK_LOW 4
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#define MCONTROL_MATCH_MASK_HIGH 5
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#define MCAUSE_INTERRUPT (1ULL<<((__riscv_xlen)-1))
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#define MIP_SSIP (1 << IRQ_S_SOFT)
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#define MIP_HSIP (1 << IRQ_H_SOFT)
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#define MIP_MSIP (1 << IRQ_M_SOFT)
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#define MIP_STIP (1 << IRQ_S_TIMER)
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#define MIP_HTIP (1 << IRQ_H_TIMER)
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#define MIP_MTIP (1 << IRQ_M_TIMER)
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#define MIP_SEIP (1 << IRQ_S_EXT)
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#define MIP_HEIP (1 << IRQ_H_EXT)
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#define MIP_MEIP (1 << IRQ_M_EXT)
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#define MIE_SSIE MIP_SSIP
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#define MIE_HSIE MIP_HSIP
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#define MIE_MSIE MIP_MSIP
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#define MIE_STIE MIP_STIP
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#define MIE_HTIE MIP_HTIP
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#define MIE_MTIE MIP_MTIP
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#define MIE_SEIE MIP_SEIP
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#define MIE_HEIE MIP_HEIP
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#define MIE_MEIE MIP_MEIP
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#define WFE_WFE 0x1
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#define MCOUNTINHIBIT_IR (1<<2)
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#define MCOUNTINHIBIT_CY (1<<0)
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#define MMISC_CTL_NMI_CAUSE_FFF (1<<9)
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#define MMISC_CTL_MISALIGN (1<<6)
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#define MMISC_CTL_BPU (1<<3)
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#define SIP_SSIP MIP_SSIP
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#define SIP_STIP MIP_STIP
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#define PRV_U 0
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#define PRV_S 1
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#define PRV_H 2
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#define PRV_M 3
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#define VM_MBARE 0
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#define VM_MBB 1
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#define VM_MBBID 2
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#define VM_SV32 8
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#define VM_SV39 9
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#define VM_SV48 10
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#define IRQ_S_SOFT 1
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#define IRQ_H_SOFT 2
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#define IRQ_M_SOFT 3
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#define IRQ_S_TIMER 5
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#define IRQ_H_TIMER 6
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#define IRQ_M_TIMER 7
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#define IRQ_S_EXT 9
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#define IRQ_H_EXT 10
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#define IRQ_M_EXT 11
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#define IRQ_COP 12
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#define IRQ_HOST 13
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#define DEFAULT_RSTVEC 0x00001000
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#define DEFAULT_NMIVEC 0x00001004
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#define DEFAULT_MTVEC 0x00001010
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#define CONFIG_STRING_ADDR 0x0000100C
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#define EXT_IO_BASE 0x40000000
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#define DRAM_BASE 0x80000000
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/* === FPU FRM Rounding Mode === */
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#define FRM_RNDMODE_RNE 0x0
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#define FRM_RNDMODE_RTZ 0x1
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#define FRM_RNDMODE_RDN 0x2
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#define FRM_RNDMODE_RUP 0x3
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#define FRM_RNDMODE_RMM 0x4
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#define FRM_RNDMODE_DYN 0x7
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/* === FPU FFLAGS Accrued Exceptions === */
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#define FFLAGS_AE_NX (1<<0)
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#define FFLAGS_AE_UF (1<<1)
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#define FFLAGS_AE_OF (1<<2)
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#define FFLAGS_AE_DZ (1<<3)
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#define FFLAGS_AE_NV (1<<4)
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#define FREG(idx) f##idx
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/* === PMP CFG Bits === */
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#define PMP_R 0x01
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#define PMP_W 0x02
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#define PMP_X 0x04
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#define PMP_A 0x18
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#define PMP_A_TOR 0x08
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#define PMP_A_NA4 0x10
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#define PMP_A_NAPOT 0x18
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#define PMP_L 0x80
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#define PMP_SHIFT 2
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#define PMP_COUNT 16
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// page table entry (PTE) fields
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#define PTE_V 0x001 // Valid
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#define PTE_R 0x002 // Read
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#define PTE_W 0x004 // Write
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#define PTE_X 0x008 // Execute
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#define PTE_U 0x010 // User
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#define PTE_G 0x020 // Global
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#define PTE_A 0x040 // Accessed
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#define PTE_D 0x080 // Dirty
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#define PTE_SOFT 0x300 // Reserved for Software
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#define PTE_PPN_SHIFT 10
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#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
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#ifdef __riscv
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#ifdef __riscv64
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# define MSTATUS_SD MSTATUS64_SD
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# define SSTATUS_SD SSTATUS64_SD
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# define RISCV_PGLEVEL_BITS 9
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#else
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# define MSTATUS_SD MSTATUS32_SD
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# define SSTATUS_SD SSTATUS32_SD
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# define RISCV_PGLEVEL_BITS 10
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#endif
/* __riscv64 */
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#define RISCV_PGSHIFT 12
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#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
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#endif
/* __riscv */
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/* === Standard RISC-V CSR Registers === */
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#define CSR_USTATUS 0x0
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#define CSR_FFLAGS 0x1
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#define CSR_FRM 0x2
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#define CSR_FCSR 0x3
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#define CSR_CYCLE 0xc00
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#define CSR_TIME 0xc01
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#define CSR_INSTRET 0xc02
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#define CSR_HPMCOUNTER3 0xc03
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#define CSR_HPMCOUNTER4 0xc04
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#define CSR_HPMCOUNTER5 0xc05
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#define CSR_HPMCOUNTER6 0xc06
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#define CSR_HPMCOUNTER7 0xc07
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#define CSR_HPMCOUNTER8 0xc08
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#define CSR_HPMCOUNTER9 0xc09
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#define CSR_HPMCOUNTER10 0xc0a
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#define CSR_HPMCOUNTER11 0xc0b
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#define CSR_HPMCOUNTER12 0xc0c
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#define CSR_HPMCOUNTER13 0xc0d
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#define CSR_HPMCOUNTER14 0xc0e
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#define CSR_HPMCOUNTER15 0xc0f
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#define CSR_HPMCOUNTER16 0xc10
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#define CSR_HPMCOUNTER17 0xc11
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#define CSR_HPMCOUNTER18 0xc12
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#define CSR_HPMCOUNTER19 0xc13
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#define CSR_HPMCOUNTER20 0xc14
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#define CSR_HPMCOUNTER21 0xc15
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#define CSR_HPMCOUNTER22 0xc16
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#define CSR_HPMCOUNTER23 0xc17
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#define CSR_HPMCOUNTER24 0xc18
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#define CSR_HPMCOUNTER25 0xc19
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#define CSR_HPMCOUNTER26 0xc1a
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#define CSR_HPMCOUNTER27 0xc1b
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#define CSR_HPMCOUNTER28 0xc1c
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#define CSR_HPMCOUNTER29 0xc1d
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#define CSR_HPMCOUNTER30 0xc1e
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#define CSR_HPMCOUNTER31 0xc1f
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#define CSR_SSTATUS 0x100
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#define CSR_SIE 0x104
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#define CSR_STVEC 0x105
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#define CSR_SSCRATCH 0x140
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#define CSR_SEPC 0x141
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#define CSR_SCAUSE 0x142
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#define CSR_SBADADDR 0x143
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#define CSR_SIP 0x144
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#define CSR_SPTBR 0x180
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#define CSR_MSTATUS 0x300
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#define CSR_MISA 0x301
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#define CSR_MEDELEG 0x302
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#define CSR_MIDELEG 0x303
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#define CSR_MIE 0x304
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#define CSR_MTVEC 0x305
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#define CSR_MCOUNTEREN 0x306
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#define CSR_MSCRATCH 0x340
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#define CSR_MEPC 0x341
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#define CSR_MCAUSE 0x342
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#define CSR_MBADADDR 0x343
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#define CSR_MIP 0x344
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#define CSR_PMPCFG0 0x3a0
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#define CSR_PMPCFG1 0x3a1
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#define CSR_PMPCFG2 0x3a2
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#define CSR_PMPCFG3 0x3a3
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#define CSR_PMPADDR0 0x3b0
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#define CSR_PMPADDR1 0x3b1
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#define CSR_PMPADDR2 0x3b2
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#define CSR_PMPADDR3 0x3b3
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#define CSR_PMPADDR4 0x3b4
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#define CSR_PMPADDR5 0x3b5
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#define CSR_PMPADDR6 0x3b6
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#define CSR_PMPADDR7 0x3b7
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#define CSR_PMPADDR8 0x3b8
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#define CSR_PMPADDR9 0x3b9
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#define CSR_PMPADDR10 0x3ba
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#define CSR_PMPADDR11 0x3bb
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#define CSR_PMPADDR12 0x3bc
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#define CSR_PMPADDR13 0x3bd
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#define CSR_PMPADDR14 0x3be
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#define CSR_PMPADDR15 0x3bf
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#define CSR_TSELECT 0x7a0
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#define CSR_TDATA1 0x7a1
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#define CSR_TDATA2 0x7a2
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#define CSR_TDATA3 0x7a3
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#define CSR_DCSR 0x7b0
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#define CSR_DPC 0x7b1
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#define CSR_DSCRATCH 0x7b2
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#define CSR_MCYCLE 0xb00
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#define CSR_MINSTRET 0xb02
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#define CSR_MHPMCOUNTER3 0xb03
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#define CSR_MHPMCOUNTER4 0xb04
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#define CSR_MHPMCOUNTER5 0xb05
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#define CSR_MHPMCOUNTER6 0xb06
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#define CSR_MHPMCOUNTER7 0xb07
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#define CSR_MHPMCOUNTER8 0xb08
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#define CSR_MHPMCOUNTER9 0xb09
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#define CSR_MHPMCOUNTER10 0xb0a
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#define CSR_MHPMCOUNTER11 0xb0b
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#define CSR_MHPMCOUNTER12 0xb0c
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#define CSR_MHPMCOUNTER13 0xb0d
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#define CSR_MHPMCOUNTER14 0xb0e
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#define CSR_MHPMCOUNTER15 0xb0f
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#define CSR_MHPMCOUNTER16 0xb10
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#define CSR_MHPMCOUNTER17 0xb11
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#define CSR_MHPMCOUNTER18 0xb12
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#define CSR_MHPMCOUNTER19 0xb13
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#define CSR_MHPMCOUNTER20 0xb14
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#define CSR_MHPMCOUNTER21 0xb15
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#define CSR_MHPMCOUNTER22 0xb16
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#define CSR_MHPMCOUNTER23 0xb17
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#define CSR_MHPMCOUNTER24 0xb18
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#define CSR_MHPMCOUNTER25 0xb19
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#define CSR_MHPMCOUNTER26 0xb1a
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#define CSR_MHPMCOUNTER27 0xb1b
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#define CSR_MHPMCOUNTER28 0xb1c
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#define CSR_MHPMCOUNTER29 0xb1d
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#define CSR_MHPMCOUNTER30 0xb1e
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#define CSR_MHPMCOUNTER31 0xb1f
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#define CSR_MUCOUNTEREN 0x320
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#define CSR_MSCOUNTEREN 0x321
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#define CSR_MHPMEVENT3 0x323
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#define CSR_MHPMEVENT4 0x324
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#define CSR_MHPMEVENT5 0x325
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#define CSR_MHPMEVENT6 0x326
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#define CSR_MHPMEVENT7 0x327
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#define CSR_MHPMEVENT8 0x328
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#define CSR_MHPMEVENT9 0x329
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#define CSR_MHPMEVENT10 0x32a
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#define CSR_MHPMEVENT11 0x32b
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#define CSR_MHPMEVENT12 0x32c
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#define CSR_MHPMEVENT13 0x32d
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#define CSR_MHPMEVENT14 0x32e
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#define CSR_MHPMEVENT15 0x32f
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#define CSR_MHPMEVENT16 0x330
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#define CSR_MHPMEVENT17 0x331
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#define CSR_MHPMEVENT18 0x332
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#define CSR_MHPMEVENT19 0x333
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#define CSR_MHPMEVENT20 0x334
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#define CSR_MHPMEVENT21 0x335
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#define CSR_MHPMEVENT22 0x336
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#define CSR_MHPMEVENT23 0x337
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#define CSR_MHPMEVENT24 0x338
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#define CSR_MHPMEVENT25 0x339
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#define CSR_MHPMEVENT26 0x33a
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#define CSR_MHPMEVENT27 0x33b
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#define CSR_MHPMEVENT28 0x33c
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#define CSR_MHPMEVENT29 0x33d
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#define CSR_MHPMEVENT30 0x33e
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#define CSR_MHPMEVENT31 0x33f
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#define CSR_MVENDORID 0xf11
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#define CSR_MARCHID 0xf12
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#define CSR_MIMPID 0xf13
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#define CSR_MHARTID 0xf14
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#define CSR_CYCLEH 0xc80
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#define CSR_TIMEH 0xc81
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#define CSR_INSTRETH 0xc82
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#define CSR_HPMCOUNTER3H 0xc83
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#define CSR_HPMCOUNTER4H 0xc84
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#define CSR_HPMCOUNTER5H 0xc85
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#define CSR_HPMCOUNTER6H 0xc86
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#define CSR_HPMCOUNTER7H 0xc87
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#define CSR_HPMCOUNTER8H 0xc88
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#define CSR_HPMCOUNTER9H 0xc89
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#define CSR_HPMCOUNTER10H 0xc8a
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#define CSR_HPMCOUNTER11H 0xc8b
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#define CSR_HPMCOUNTER12H 0xc8c
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#define CSR_HPMCOUNTER13H 0xc8d
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#define CSR_HPMCOUNTER14H 0xc8e
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#define CSR_HPMCOUNTER15H 0xc8f
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#define CSR_HPMCOUNTER16H 0xc90
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#define CSR_HPMCOUNTER17H 0xc91
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#define CSR_HPMCOUNTER18H 0xc92
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#define CSR_HPMCOUNTER19H 0xc93
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#define CSR_HPMCOUNTER20H 0xc94
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#define CSR_HPMCOUNTER21H 0xc95
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#define CSR_HPMCOUNTER22H 0xc96
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#define CSR_HPMCOUNTER23H 0xc97
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#define CSR_HPMCOUNTER24H 0xc98
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#define CSR_HPMCOUNTER25H 0xc99
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#define CSR_HPMCOUNTER26H 0xc9a
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#define CSR_HPMCOUNTER27H 0xc9b
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#define CSR_HPMCOUNTER28H 0xc9c
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#define CSR_HPMCOUNTER29H 0xc9d
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#define CSR_HPMCOUNTER30H 0xc9e
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#define CSR_HPMCOUNTER31H 0xc9f
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#define CSR_MCYCLEH 0xb80
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#define CSR_MINSTRETH 0xb82
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#define CSR_MHPMCOUNTER3H 0xb83
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#define CSR_MHPMCOUNTER4H 0xb84
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#define CSR_MHPMCOUNTER5H 0xb85
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#define CSR_MHPMCOUNTER6H 0xb86
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#define CSR_MHPMCOUNTER7H 0xb87
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#define CSR_MHPMCOUNTER8H 0xb88
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#define CSR_MHPMCOUNTER9H 0xb89
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#define CSR_MHPMCOUNTER10H 0xb8a
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#define CSR_MHPMCOUNTER11H 0xb8b
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#define CSR_MHPMCOUNTER12H 0xb8c
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#define CSR_MHPMCOUNTER13H 0xb8d
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#define CSR_MHPMCOUNTER14H 0xb8e
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#define CSR_MHPMCOUNTER15H 0xb8f
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#define CSR_MHPMCOUNTER16H 0xb90
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#define CSR_MHPMCOUNTER17H 0xb91
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#define CSR_MHPMCOUNTER18H 0xb92
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#define CSR_MHPMCOUNTER19H 0xb93
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#define CSR_MHPMCOUNTER20H 0xb94
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#define CSR_MHPMCOUNTER21H 0xb95
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#define CSR_MHPMCOUNTER22H 0xb96
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#define CSR_MHPMCOUNTER23H 0xb97
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#define CSR_MHPMCOUNTER24H 0xb98
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#define CSR_MHPMCOUNTER25H 0xb99
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#define CSR_MHPMCOUNTER26H 0xb9a
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#define CSR_MHPMCOUNTER27H 0xb9b
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#define CSR_MHPMCOUNTER28H 0xb9c
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#define CSR_MHPMCOUNTER29H 0xb9d
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#define CSR_MHPMCOUNTER30H 0xb9e
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#define CSR_MHPMCOUNTER31H 0xb9f
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/* === CLIC CSR Registers === */
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#define CSR_MTVT 0x307
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#define CSR_MNXTI 0x345
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#define CSR_MINTSTATUS 0x346
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#define CSR_MSCRATCHCSW 0x348
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#define CSR_MSCRATCHCSWL 0x349
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#define CSR_MCLICBASE 0x350
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/* === Nuclei custom CSR Registers === */
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#define CSR_MCOUNTINHIBIT 0x320
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#define CSR_MNVEC 0x7C3
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#define CSR_MSUBM 0x7C4
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#define CSR_MDCAUSE 0x7C9
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#define CSR_MCACHE_CTL 0x7CA
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#define CSR_MMISC_CTL 0x7D0
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#define CSR_MSAVESTATUS 0x7D6
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#define CSR_MSAVEEPC1 0x7D7
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#define CSR_MSAVECAUSE1 0x7D8
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#define CSR_MSAVEEPC2 0x7D9
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#define CSR_MSAVECAUSE2 0x7DA
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#define CSR_MSAVEDCAUSE1 0x7DB
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#define CSR_MSAVEDCAUSE2 0x7DC
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#define CSR_PUSHMSUBM 0x7EB
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#define CSR_MTVT2 0x7EC
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#define CSR_JALMNXTI 0x7ED
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#define CSR_PUSHMCAUSE 0x7EE
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#define CSR_PUSHMEPC 0x7EF
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#define CSR_SLEEPVALUE 0x811
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#define CSR_TXEVT 0x812
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#define CSR_WFE 0x810
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/* Exception Code in MCAUSE CSR */
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#define CAUSE_MISALIGNED_FETCH 0x0
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#define CAUSE_FAULT_FETCH 0x1
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#define CAUSE_ILLEGAL_INSTRUCTION 0x2
529
#define CAUSE_BREAKPOINT 0x3
530
#define CAUSE_MISALIGNED_LOAD 0x4
531
#define CAUSE_FAULT_LOAD 0x5
532
#define CAUSE_MISALIGNED_STORE 0x6
533
#define CAUSE_FAULT_STORE 0x7
534
#define CAUSE_USER_ECALL 0x8
535
#define CAUSE_SUPERVISOR_ECALL 0x9
536
#define CAUSE_HYPERVISOR_ECALL 0xa
537
#define CAUSE_MACHINE_ECALL 0xb
538
539
/* Exception Subcode in MDCAUSE CSR */
540
#define DCAUSE_FAULT_FETCH_PMP 0x1
541
#define DCAUSE_FAULT_FETCH_INST 0x2
542
543
#define DCAUSE_FAULT_LOAD_PMP 0x1
544
#define DCAUSE_FAULT_LOAD_INST 0x2
545
#define DCAUSE_FAULT_LOAD_NICE 0x3
546
547
#define DCAUSE_FAULT_STORE_PMP 0x1
548
#define DCAUSE_FAULT_STORE_INST 0x2
549
552
#ifdef __cplusplus
553
}
554
#endif
555
#endif
/* __RISCV_ENCODING_H__ */
NMSIS
Core
Include
riscv_encoding.h
Generated on Wed Jan 18 2023 06:37:35 for NMSIS-Core by
1.8.17