NMSIS-Core  Version 1.0.0-HummingBird
NMSIS-Core support for HummingBird RISC-V processor-based devices
riscv_encoding.h
1 /*
2  * Copyright (c) 2019 Nuclei Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Licensed under the Apache License, Version 2.0 (the License); you may
7  * not use this file except in compliance with the License.
8  * You may obtain a copy of the License at
9  *
10  * www.apache.org/licenses/LICENSE-2.0
11  *
12  * Unless required by applicable law or agreed to in writing, software
13  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15  * See the License for the specific language governing permissions and
16  * limitations under the License.
17  */
18 #ifndef __RISCV_ENCODING_H__
19 #define __RISCV_ENCODING_H__
20 
21 #include "riscv_bits.h"
22 #ifdef __cplusplus
23  extern "C" {
24 #endif
25 
34 #define MSTATUS_UIE 0x00000001
35 #define MSTATUS_SIE 0x00000002
36 #define MSTATUS_HIE 0x00000004
37 #define MSTATUS_MIE 0x00000008
38 #define MSTATUS_UPIE 0x00000010
39 #define MSTATUS_SPIE 0x00000020
40 #define MSTATUS_HPIE 0x00000040
41 #define MSTATUS_MPIE 0x00000080
42 #define MSTATUS_SPP 0x00000100
43 #define MSTATUS_MPP 0x00001800
44 #define MSTATUS_FS 0x00006000
45 #define MSTATUS_XS 0x00018000
46 #define MSTATUS_MPRV 0x00020000
47 #define MSTATUS_PUM 0x00040000
48 #define MSTATUS_MXR 0x00080000
49 #define MSTATUS_VM 0x1F000000
50 #define MSTATUS32_SD 0x80000000
51 #define MSTATUS64_SD 0x8000000000000000
52 
53 #define MSTATUS_FS_INITIAL 0x00002000
54 #define MSTATUS_FS_CLEAN 0x00004000
55 #define MSTATUS_FS_DIRTY 0x00006000
56 
57 #define SSTATUS_UIE 0x00000001
58 #define SSTATUS_SIE 0x00000002
59 #define SSTATUS_UPIE 0x00000010
60 #define SSTATUS_SPIE 0x00000020
61 #define SSTATUS_SPP 0x00000100
62 #define SSTATUS_FS 0x00006000
63 #define SSTATUS_XS 0x00018000
64 #define SSTATUS_PUM 0x00040000
65 #define SSTATUS32_SD 0x80000000
66 #define SSTATUS64_SD 0x8000000000000000
67 
68 #define CSR_MCACHE_CTL_IE 0x00000001
69 #define CSR_MCACHE_CTL_DE 0x00010000
70 
71 #define DCSR_XDEBUGVER (3U<<30)
72 #define DCSR_NDRESET (1<<29)
73 #define DCSR_FULLRESET (1<<28)
74 #define DCSR_EBREAKM (1<<15)
75 #define DCSR_EBREAKH (1<<14)
76 #define DCSR_EBREAKS (1<<13)
77 #define DCSR_EBREAKU (1<<12)
78 #define DCSR_STOPCYCLE (1<<10)
79 #define DCSR_STOPTIME (1<<9)
80 #define DCSR_CAUSE (7<<6)
81 #define DCSR_DEBUGINT (1<<5)
82 #define DCSR_HALT (1<<3)
83 #define DCSR_STEP (1<<2)
84 #define DCSR_PRV (3<<0)
85 
86 #define DCSR_CAUSE_NONE 0
87 #define DCSR_CAUSE_SWBP 1
88 #define DCSR_CAUSE_HWBP 2
89 #define DCSR_CAUSE_DEBUGINT 3
90 #define DCSR_CAUSE_STEP 4
91 #define DCSR_CAUSE_HALT 5
92 
93 #define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))
94 #define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))
95 #define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
96 
97 #define MCONTROL_SELECT (1<<19)
98 #define MCONTROL_TIMING (1<<18)
99 #define MCONTROL_ACTION (0x3f<<12)
100 #define MCONTROL_CHAIN (1<<11)
101 #define MCONTROL_MATCH (0xf<<7)
102 #define MCONTROL_M (1<<6)
103 #define MCONTROL_H (1<<5)
104 #define MCONTROL_S (1<<4)
105 #define MCONTROL_U (1<<3)
106 #define MCONTROL_EXECUTE (1<<2)
107 #define MCONTROL_STORE (1<<1)
108 #define MCONTROL_LOAD (1<<0)
109 
110 #define MCONTROL_TYPE_NONE 0
111 #define MCONTROL_TYPE_MATCH 2
112 
113 #define MCONTROL_ACTION_DEBUG_EXCEPTION 0
114 #define MCONTROL_ACTION_DEBUG_MODE 1
115 #define MCONTROL_ACTION_TRACE_START 2
116 #define MCONTROL_ACTION_TRACE_STOP 3
117 #define MCONTROL_ACTION_TRACE_EMIT 4
118 
119 #define MCONTROL_MATCH_EQUAL 0
120 #define MCONTROL_MATCH_NAPOT 1
121 #define MCONTROL_MATCH_GE 2
122 #define MCONTROL_MATCH_LT 3
123 #define MCONTROL_MATCH_MASK_LOW 4
124 #define MCONTROL_MATCH_MASK_HIGH 5
125 
126 #define MCAUSE_INTERRUPT (1ULL<<((__riscv_xlen)-1))
127 
128 #define MIP_SSIP (1 << IRQ_S_SOFT)
129 #define MIP_HSIP (1 << IRQ_H_SOFT)
130 #define MIP_MSIP (1 << IRQ_M_SOFT)
131 #define MIP_STIP (1 << IRQ_S_TIMER)
132 #define MIP_HTIP (1 << IRQ_H_TIMER)
133 #define MIP_MTIP (1 << IRQ_M_TIMER)
134 #define MIP_SEIP (1 << IRQ_S_EXT)
135 #define MIP_HEIP (1 << IRQ_H_EXT)
136 #define MIP_MEIP (1 << IRQ_M_EXT)
137 
138 #define MIE_SSIE MIP_SSIP
139 #define MIE_HSIE MIP_HSIP
140 #define MIE_MSIE MIP_MSIP
141 #define MIE_STIE MIP_STIP
142 #define MIE_HTIE MIP_HTIP
143 #define MIE_MTIE MIP_MTIP
144 #define MIE_SEIE MIP_SEIP
145 #define MIE_HEIE MIP_HEIP
146 #define MIE_MEIE MIP_MEIP
147 
148 #define WFE_WFE 0x1
149 
150 #define MCOUNTINHIBIT_IR (1<<2)
151 #define MCOUNTINHIBIT_CY (1<<0)
152 
153 #define MMISC_CTL_NMI_CAUSE_FFF (1<<9)
154 #define MMISC_CTL_MISALIGN (1<<6)
155 #define MMISC_CTL_BPU (1<<3)
156 
157 #define SIP_SSIP MIP_SSIP
158 #define SIP_STIP MIP_STIP
159 
160 #define PRV_U 0
161 #define PRV_S 1
162 #define PRV_H 2
163 #define PRV_M 3
164 
165 #define VM_MBARE 0
166 #define VM_MBB 1
167 #define VM_MBBID 2
168 #define VM_SV32 8
169 #define VM_SV39 9
170 #define VM_SV48 10
171 
172 #define IRQ_S_SOFT 1
173 #define IRQ_H_SOFT 2
174 #define IRQ_M_SOFT 3
175 #define IRQ_S_TIMER 5
176 #define IRQ_H_TIMER 6
177 #define IRQ_M_TIMER 7
178 #define IRQ_S_EXT 9
179 #define IRQ_H_EXT 10
180 #define IRQ_M_EXT 11
181 #define IRQ_COP 12
182 #define IRQ_HOST 13
183 
184 #define DEFAULT_RSTVEC 0x00001000
185 #define DEFAULT_NMIVEC 0x00001004
186 #define DEFAULT_MTVEC 0x00001010
187 #define CONFIG_STRING_ADDR 0x0000100C
188 #define EXT_IO_BASE 0x40000000
189 #define DRAM_BASE 0x80000000
190 
191 /* === FPU FRM Rounding Mode === */
193 #define FRM_RNDMODE_RNE 0x0
194 
195 #define FRM_RNDMODE_RTZ 0x1
196 
197 #define FRM_RNDMODE_RDN 0x2
198 
199 #define FRM_RNDMODE_RUP 0x3
200 
201 #define FRM_RNDMODE_RMM 0x4
202 
205 #define FRM_RNDMODE_DYN 0x7
206 
207 /* === FPU FFLAGS Accrued Exceptions === */
209 #define FFLAGS_AE_NX (1<<0)
210 
211 #define FFLAGS_AE_UF (1<<1)
212 
213 #define FFLAGS_AE_OF (1<<2)
214 
215 #define FFLAGS_AE_DZ (1<<3)
216 
217 #define FFLAGS_AE_NV (1<<4)
218 
220 #define FREG(idx) f##idx
221 
222 
223 /* === PMP CFG Bits === */
224 #define PMP_R 0x01
225 #define PMP_W 0x02
226 #define PMP_X 0x04
227 #define PMP_A 0x18
228 #define PMP_A_TOR 0x08
229 #define PMP_A_NA4 0x10
230 #define PMP_A_NAPOT 0x18
231 #define PMP_L 0x80
232 
233 #define PMP_SHIFT 2
234 #define PMP_COUNT 16
235 
236 // page table entry (PTE) fields
237 #define PTE_V 0x001 // Valid
238 #define PTE_R 0x002 // Read
239 #define PTE_W 0x004 // Write
240 #define PTE_X 0x008 // Execute
241 #define PTE_U 0x010 // User
242 #define PTE_G 0x020 // Global
243 #define PTE_A 0x040 // Accessed
244 #define PTE_D 0x080 // Dirty
245 #define PTE_SOFT 0x300 // Reserved for Software
246 
247 #define PTE_PPN_SHIFT 10
248 
249 #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
250 
251 #ifdef __riscv
252 
253 #ifdef __riscv64
254 # define MSTATUS_SD MSTATUS64_SD
255 # define SSTATUS_SD SSTATUS64_SD
256 # define RISCV_PGLEVEL_BITS 9
257 #else
258 # define MSTATUS_SD MSTATUS32_SD
259 # define SSTATUS_SD SSTATUS32_SD
260 # define RISCV_PGLEVEL_BITS 10
261 #endif /* __riscv64 */
262 
263 #define RISCV_PGSHIFT 12
264 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
265 
266 #endif /* __riscv */
267 
277 /* === Standard RISC-V CSR Registers === */
278 #define CSR_USTATUS 0x0
279 #define CSR_FFLAGS 0x1
280 #define CSR_FRM 0x2
281 #define CSR_FCSR 0x3
282 #define CSR_CYCLE 0xc00
283 #define CSR_TIME 0xc01
284 #define CSR_INSTRET 0xc02
285 #define CSR_HPMCOUNTER3 0xc03
286 #define CSR_HPMCOUNTER4 0xc04
287 #define CSR_HPMCOUNTER5 0xc05
288 #define CSR_HPMCOUNTER6 0xc06
289 #define CSR_HPMCOUNTER7 0xc07
290 #define CSR_HPMCOUNTER8 0xc08
291 #define CSR_HPMCOUNTER9 0xc09
292 #define CSR_HPMCOUNTER10 0xc0a
293 #define CSR_HPMCOUNTER11 0xc0b
294 #define CSR_HPMCOUNTER12 0xc0c
295 #define CSR_HPMCOUNTER13 0xc0d
296 #define CSR_HPMCOUNTER14 0xc0e
297 #define CSR_HPMCOUNTER15 0xc0f
298 #define CSR_HPMCOUNTER16 0xc10
299 #define CSR_HPMCOUNTER17 0xc11
300 #define CSR_HPMCOUNTER18 0xc12
301 #define CSR_HPMCOUNTER19 0xc13
302 #define CSR_HPMCOUNTER20 0xc14
303 #define CSR_HPMCOUNTER21 0xc15
304 #define CSR_HPMCOUNTER22 0xc16
305 #define CSR_HPMCOUNTER23 0xc17
306 #define CSR_HPMCOUNTER24 0xc18
307 #define CSR_HPMCOUNTER25 0xc19
308 #define CSR_HPMCOUNTER26 0xc1a
309 #define CSR_HPMCOUNTER27 0xc1b
310 #define CSR_HPMCOUNTER28 0xc1c
311 #define CSR_HPMCOUNTER29 0xc1d
312 #define CSR_HPMCOUNTER30 0xc1e
313 #define CSR_HPMCOUNTER31 0xc1f
314 #define CSR_SSTATUS 0x100
315 #define CSR_SIE 0x104
316 #define CSR_STVEC 0x105
317 #define CSR_SSCRATCH 0x140
318 #define CSR_SEPC 0x141
319 #define CSR_SCAUSE 0x142
320 #define CSR_SBADADDR 0x143
321 #define CSR_SIP 0x144
322 #define CSR_SPTBR 0x180
323 #define CSR_MSTATUS 0x300
324 #define CSR_MISA 0x301
325 #define CSR_MEDELEG 0x302
326 #define CSR_MIDELEG 0x303
327 #define CSR_MIE 0x304
328 #define CSR_MTVEC 0x305
329 #define CSR_MCOUNTEREN 0x306
330 #define CSR_MSCRATCH 0x340
331 #define CSR_MEPC 0x341
332 #define CSR_MCAUSE 0x342
333 #define CSR_MBADADDR 0x343
334 #define CSR_MIP 0x344
335 #define CSR_PMPCFG0 0x3a0
336 #define CSR_PMPCFG1 0x3a1
337 #define CSR_PMPCFG2 0x3a2
338 #define CSR_PMPCFG3 0x3a3
339 #define CSR_PMPADDR0 0x3b0
340 #define CSR_PMPADDR1 0x3b1
341 #define CSR_PMPADDR2 0x3b2
342 #define CSR_PMPADDR3 0x3b3
343 #define CSR_PMPADDR4 0x3b4
344 #define CSR_PMPADDR5 0x3b5
345 #define CSR_PMPADDR6 0x3b6
346 #define CSR_PMPADDR7 0x3b7
347 #define CSR_PMPADDR8 0x3b8
348 #define CSR_PMPADDR9 0x3b9
349 #define CSR_PMPADDR10 0x3ba
350 #define CSR_PMPADDR11 0x3bb
351 #define CSR_PMPADDR12 0x3bc
352 #define CSR_PMPADDR13 0x3bd
353 #define CSR_PMPADDR14 0x3be
354 #define CSR_PMPADDR15 0x3bf
355 #define CSR_TSELECT 0x7a0
356 #define CSR_TDATA1 0x7a1
357 #define CSR_TDATA2 0x7a2
358 #define CSR_TDATA3 0x7a3
359 #define CSR_DCSR 0x7b0
360 #define CSR_DPC 0x7b1
361 #define CSR_DSCRATCH 0x7b2
362 #define CSR_MCYCLE 0xb00
363 #define CSR_MINSTRET 0xb02
364 #define CSR_MHPMCOUNTER3 0xb03
365 #define CSR_MHPMCOUNTER4 0xb04
366 #define CSR_MHPMCOUNTER5 0xb05
367 #define CSR_MHPMCOUNTER6 0xb06
368 #define CSR_MHPMCOUNTER7 0xb07
369 #define CSR_MHPMCOUNTER8 0xb08
370 #define CSR_MHPMCOUNTER9 0xb09
371 #define CSR_MHPMCOUNTER10 0xb0a
372 #define CSR_MHPMCOUNTER11 0xb0b
373 #define CSR_MHPMCOUNTER12 0xb0c
374 #define CSR_MHPMCOUNTER13 0xb0d
375 #define CSR_MHPMCOUNTER14 0xb0e
376 #define CSR_MHPMCOUNTER15 0xb0f
377 #define CSR_MHPMCOUNTER16 0xb10
378 #define CSR_MHPMCOUNTER17 0xb11
379 #define CSR_MHPMCOUNTER18 0xb12
380 #define CSR_MHPMCOUNTER19 0xb13
381 #define CSR_MHPMCOUNTER20 0xb14
382 #define CSR_MHPMCOUNTER21 0xb15
383 #define CSR_MHPMCOUNTER22 0xb16
384 #define CSR_MHPMCOUNTER23 0xb17
385 #define CSR_MHPMCOUNTER24 0xb18
386 #define CSR_MHPMCOUNTER25 0xb19
387 #define CSR_MHPMCOUNTER26 0xb1a
388 #define CSR_MHPMCOUNTER27 0xb1b
389 #define CSR_MHPMCOUNTER28 0xb1c
390 #define CSR_MHPMCOUNTER29 0xb1d
391 #define CSR_MHPMCOUNTER30 0xb1e
392 #define CSR_MHPMCOUNTER31 0xb1f
393 #define CSR_MUCOUNTEREN 0x320
394 #define CSR_MSCOUNTEREN 0x321
395 #define CSR_MHPMEVENT3 0x323
396 #define CSR_MHPMEVENT4 0x324
397 #define CSR_MHPMEVENT5 0x325
398 #define CSR_MHPMEVENT6 0x326
399 #define CSR_MHPMEVENT7 0x327
400 #define CSR_MHPMEVENT8 0x328
401 #define CSR_MHPMEVENT9 0x329
402 #define CSR_MHPMEVENT10 0x32a
403 #define CSR_MHPMEVENT11 0x32b
404 #define CSR_MHPMEVENT12 0x32c
405 #define CSR_MHPMEVENT13 0x32d
406 #define CSR_MHPMEVENT14 0x32e
407 #define CSR_MHPMEVENT15 0x32f
408 #define CSR_MHPMEVENT16 0x330
409 #define CSR_MHPMEVENT17 0x331
410 #define CSR_MHPMEVENT18 0x332
411 #define CSR_MHPMEVENT19 0x333
412 #define CSR_MHPMEVENT20 0x334
413 #define CSR_MHPMEVENT21 0x335
414 #define CSR_MHPMEVENT22 0x336
415 #define CSR_MHPMEVENT23 0x337
416 #define CSR_MHPMEVENT24 0x338
417 #define CSR_MHPMEVENT25 0x339
418 #define CSR_MHPMEVENT26 0x33a
419 #define CSR_MHPMEVENT27 0x33b
420 #define CSR_MHPMEVENT28 0x33c
421 #define CSR_MHPMEVENT29 0x33d
422 #define CSR_MHPMEVENT30 0x33e
423 #define CSR_MHPMEVENT31 0x33f
424 #define CSR_MVENDORID 0xf11
425 #define CSR_MARCHID 0xf12
426 #define CSR_MIMPID 0xf13
427 #define CSR_MHARTID 0xf14
428 #define CSR_CYCLEH 0xc80
429 #define CSR_TIMEH 0xc81
430 #define CSR_INSTRETH 0xc82
431 #define CSR_HPMCOUNTER3H 0xc83
432 #define CSR_HPMCOUNTER4H 0xc84
433 #define CSR_HPMCOUNTER5H 0xc85
434 #define CSR_HPMCOUNTER6H 0xc86
435 #define CSR_HPMCOUNTER7H 0xc87
436 #define CSR_HPMCOUNTER8H 0xc88
437 #define CSR_HPMCOUNTER9H 0xc89
438 #define CSR_HPMCOUNTER10H 0xc8a
439 #define CSR_HPMCOUNTER11H 0xc8b
440 #define CSR_HPMCOUNTER12H 0xc8c
441 #define CSR_HPMCOUNTER13H 0xc8d
442 #define CSR_HPMCOUNTER14H 0xc8e
443 #define CSR_HPMCOUNTER15H 0xc8f
444 #define CSR_HPMCOUNTER16H 0xc90
445 #define CSR_HPMCOUNTER17H 0xc91
446 #define CSR_HPMCOUNTER18H 0xc92
447 #define CSR_HPMCOUNTER19H 0xc93
448 #define CSR_HPMCOUNTER20H 0xc94
449 #define CSR_HPMCOUNTER21H 0xc95
450 #define CSR_HPMCOUNTER22H 0xc96
451 #define CSR_HPMCOUNTER23H 0xc97
452 #define CSR_HPMCOUNTER24H 0xc98
453 #define CSR_HPMCOUNTER25H 0xc99
454 #define CSR_HPMCOUNTER26H 0xc9a
455 #define CSR_HPMCOUNTER27H 0xc9b
456 #define CSR_HPMCOUNTER28H 0xc9c
457 #define CSR_HPMCOUNTER29H 0xc9d
458 #define CSR_HPMCOUNTER30H 0xc9e
459 #define CSR_HPMCOUNTER31H 0xc9f
460 #define CSR_MCYCLEH 0xb80
461 #define CSR_MINSTRETH 0xb82
462 #define CSR_MHPMCOUNTER3H 0xb83
463 #define CSR_MHPMCOUNTER4H 0xb84
464 #define CSR_MHPMCOUNTER5H 0xb85
465 #define CSR_MHPMCOUNTER6H 0xb86
466 #define CSR_MHPMCOUNTER7H 0xb87
467 #define CSR_MHPMCOUNTER8H 0xb88
468 #define CSR_MHPMCOUNTER9H 0xb89
469 #define CSR_MHPMCOUNTER10H 0xb8a
470 #define CSR_MHPMCOUNTER11H 0xb8b
471 #define CSR_MHPMCOUNTER12H 0xb8c
472 #define CSR_MHPMCOUNTER13H 0xb8d
473 #define CSR_MHPMCOUNTER14H 0xb8e
474 #define CSR_MHPMCOUNTER15H 0xb8f
475 #define CSR_MHPMCOUNTER16H 0xb90
476 #define CSR_MHPMCOUNTER17H 0xb91
477 #define CSR_MHPMCOUNTER18H 0xb92
478 #define CSR_MHPMCOUNTER19H 0xb93
479 #define CSR_MHPMCOUNTER20H 0xb94
480 #define CSR_MHPMCOUNTER21H 0xb95
481 #define CSR_MHPMCOUNTER22H 0xb96
482 #define CSR_MHPMCOUNTER23H 0xb97
483 #define CSR_MHPMCOUNTER24H 0xb98
484 #define CSR_MHPMCOUNTER25H 0xb99
485 #define CSR_MHPMCOUNTER26H 0xb9a
486 #define CSR_MHPMCOUNTER27H 0xb9b
487 #define CSR_MHPMCOUNTER28H 0xb9c
488 #define CSR_MHPMCOUNTER29H 0xb9d
489 #define CSR_MHPMCOUNTER30H 0xb9e
490 #define CSR_MHPMCOUNTER31H 0xb9f
491 
492 /* === CLIC CSR Registers === */
493 #define CSR_MTVT 0x307
494 #define CSR_MNXTI 0x345
495 #define CSR_MINTSTATUS 0x346
496 #define CSR_MSCRATCHCSW 0x348
497 #define CSR_MSCRATCHCSWL 0x349
498 #define CSR_MCLICBASE 0x350
499 
500 /* === Nuclei custom CSR Registers === */
501 #define CSR_MCOUNTINHIBIT 0x320
502 #define CSR_MNVEC 0x7C3
503 #define CSR_MSUBM 0x7C4
504 #define CSR_MDCAUSE 0x7C9
505 #define CSR_MCACHE_CTL 0x7CA
506 #define CSR_MMISC_CTL 0x7D0
507 #define CSR_MSAVESTATUS 0x7D6
508 #define CSR_MSAVEEPC1 0x7D7
509 #define CSR_MSAVECAUSE1 0x7D8
510 #define CSR_MSAVEEPC2 0x7D9
511 #define CSR_MSAVECAUSE2 0x7DA
512 #define CSR_MSAVEDCAUSE1 0x7DB
513 #define CSR_MSAVEDCAUSE2 0x7DC
514 #define CSR_PUSHMSUBM 0x7EB
515 #define CSR_MTVT2 0x7EC
516 #define CSR_JALMNXTI 0x7ED
517 #define CSR_PUSHMCAUSE 0x7EE
518 #define CSR_PUSHMEPC 0x7EF
519 #define CSR_SLEEPVALUE 0x811
520 #define CSR_TXEVT 0x812
521 #define CSR_WFE 0x810
522 
525 /* Exception Code in MCAUSE CSR */
526 #define CAUSE_MISALIGNED_FETCH 0x0
527 #define CAUSE_FAULT_FETCH 0x1
528 #define CAUSE_ILLEGAL_INSTRUCTION 0x2
529 #define CAUSE_BREAKPOINT 0x3
530 #define CAUSE_MISALIGNED_LOAD 0x4
531 #define CAUSE_FAULT_LOAD 0x5
532 #define CAUSE_MISALIGNED_STORE 0x6
533 #define CAUSE_FAULT_STORE 0x7
534 #define CAUSE_USER_ECALL 0x8
535 #define CAUSE_SUPERVISOR_ECALL 0x9
536 #define CAUSE_HYPERVISOR_ECALL 0xa
537 #define CAUSE_MACHINE_ECALL 0xb
538 
539 /* Exception Subcode in MDCAUSE CSR */
540 #define DCAUSE_FAULT_FETCH_PMP 0x1
541 #define DCAUSE_FAULT_FETCH_INST 0x2
542 
543 #define DCAUSE_FAULT_LOAD_PMP 0x1
544 #define DCAUSE_FAULT_LOAD_INST 0x2
545 #define DCAUSE_FAULT_LOAD_NICE 0x3
546 
547 #define DCAUSE_FAULT_STORE_PMP 0x1
548 #define DCAUSE_FAULT_STORE_INST 0x2
549 
552 #ifdef __cplusplus
553 }
554 #endif
555 #endif /* __RISCV_ENCODING_H__ */