.. _eclic_plic_conn:

ECLIC and PLIC Connection Diagram
=================================

The ECLIC and PLIC are independently configurable, so they can be
co-existed or not, depends on configurations. The key points are as
followings:

-  For the single-core real-time or micro-controller applications, it is
   recommended to just have ECLIC configured, as depicted in
   :ref:`figure_eclic_plic_conn_1`.

-  For the single-core Linux capable applications, it is recommended to
   configure PLIC. But in this case, the ECLIC can also be configured,
   hence, PLIC and ECLIC become coexisting.

   -  If the ECLIC is enabled by software, then the interrupts will be
      handled by ECLIC, and the PLIC will be bypassed, as depicted in
      :ref:`figure_eclic_plic_conn_2`.

      -  In this mode, the hardware of UX class core can also worked as
         microcontroller, i.e., Nuclei UX class core is
         downward-compatible to Nuclei NX class core.

   -  If the ECLIC is disabled by software, then the interrupts will be
      handled by PLIC, and the ECLIC will be bypassed, as depicted in
      :ref:`figure_eclic_plic_conn_3`.

-  For the symmetric multi-processor (SMP) Linux capable applications,
   it is recommended to just have PLIC configured only, as depicted in
   :ref:`figure_eclic_plic_conn_4`.

Single-core with ECLIC configured only
--------------------------------------

The following figure :ref:`figure_eclic_plic_conn_1` is for single-core
with ECLIC unit configured only.

.. _figure_eclic_plic_conn_1:

.. figure:: /asserts/media/image030.png
   :width: 80 %
   :align: center
   :alt: Interrupt Connection (for single-core with ECLIC configured only)

   Interrupt Connection (for single-core with ECLIC configured only)

.. _eclic_plic_conn_single_core_plic:

Single-core with PLIC/ECLIC configured and PLIC enabled
-------------------------------------------------------

The following figure :ref:`figure_eclic_plic_conn_2` is for single-core
with PLIC/ECLIC configured and PLIC enabled.

.. _figure_eclic_plic_conn_2:

.. figure:: /asserts/media/image031.png
   :width: 80 %
   :align: center
   :alt: Interrupt Connection (for single-core with PLIC/ECLIC configured and PLIC enabled)

   Interrupt Connection (for single-core with PLIC/ECLIC configured and PLIC enabled)

.. _eclic_plic_conn_single_core_eclic:

Single-core with PLIC/ECLIC configured and ECLIC enabled
--------------------------------------------------------

The following figure :ref:`figure_eclic_plic_conn_3` is for single-core
with PLIC/ECLIC configured and ECLIC enabled.

.. _figure_eclic_plic_conn_3:

.. figure:: /asserts/media/image032.png
   :width: 80 %
   :align: center
   :alt: Interrupt Connection (for single-core with PLIC/ECLIC configured and ECLIC enabled)

   Interrupt Connection (for single-core with PLIC/ECLIC configured and ECLIC enabled)

Multi-core with PLIC configured only
------------------------------------

The following figure :ref:`figure_eclic_plic_conn_4` is for Multi-core with PLIC configured only.

.. _figure_eclic_plic_conn_4:

.. figure:: /asserts/media/image033.png
   :width: 80 %
   :align: center
   :alt: Interrupt Connection (for multi-core with PLIC configured only)

   Interrupt Connection (for multi-core with PLIC configured only)